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STA333ML
Sound TerminalTM 2-channel microless high-efficiency digital audio system
Features
! ! ! ! ! ! ! ! ! ! ! ! ! ! !
Wide supply voltage range (4.5 - 18 V) 2 x 20 W into 8 at Vcc = 18 V 3 power output configurations; 2 channels of ternary PWM PowerSSO-36 exposed pad package 2 channels of 24-Bit DDX(R) 100-dB SNR and dynamic range 32 kHz to 48 kHz input sample rates Soft volume update Automatic zero-detect mute Automatic invalid input detect mute 2-channel I2S input data interface Selectable clock input ratio (256 or 364 x fs) Max power correction for lower full power 96 kHz internal processing sample rate, 24-bit precision Thermal overload and short-circuit protection embedded
PowerSSO-36 slug down
Description
STA333ML is a single die embedding digital audio processing and high efficiency DDX(R) power amplification, capable of operating without the aid of an external micro controller. The STA333ML is part of the Sound TerminalTM family that provides full digital audio streaming to the speaker offering cost effectiveness, low energy dissipation and sound enrichment. The STA333ML combines a unique 24-bit DDX(R) digital class-D ternary modulator together with an extremely low RDSON stereo power DMOS stage. It is capable of a total output power of 2 x 20 W with outstanding performance in terms of efficiency (>90 %), THD, SNR and EMI. The microless feature allows the use in low-cost applications (cradle, digital speakers, audio terminals) where no micro controller is needed. The serial audio data interface accepts the universally used I2S format. Basic features (like oversampling clock, gain and I2S format) can be set using a minimal number of selection pins. The STA333ML is self-protected against thermal overload, overcurrent, short circuit and overvoltage conditions. The fault condition is also exported to an external pin (INT_LINE) for specific requirements.
Applications
! ! ! ! !
LCD DVD Cradle Digital speaker Wireless speaker cradle
Table 1.
STA333ML
Device summary
Order code Package PowerSSO-36 (slug down) PowerSSO-36 (slug down) Tube Tape and reel Packaging
STA333ML13TR
May 2008
Rev 2
1/14
www.st.com 14
Block diagram
STA333ML
1
Block diagram
Figure 1. Block diagram
IS interface
2
Protection current/thermal Channel 1A
Volume control
Power control DDX
Logic
Channel 1B
Channel 2A
Regulators PLL Bias Channel 2B
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STA333ML
Pin description
2
Pin description
Figure 2. Pin connection (top view)
GND_SUB FMT TEST_MODE VSS_REG VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD_REG CONFIG N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VDD_DIG GND_DIG GAIN ONSEL INT_LINE RESET SDI LRCKI BICKI XTI PLL_GND FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG N.C. N.C.
Table 2.
Pin 1 2 3 4 5 6 7 8 9 10 11 12
Pin description
Type Gnd I I I/O I/O O Gnd Power O O Power Gnd Name GND_SUB FMT TEST_MODE VSS VSS_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 Substrate ground 0: I2S format 1: left justified This pin must be connected to ground Internal reference at Vcc-3.3 V Internal Vcc reference Output half bridge 2B Power negative supply Power positive supply Output half bridge 2A Output half bridge 1B Power positive supply Power negative supply Description
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Pin description Table 2.
Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Power GND I Power I GND I I I I I O I
STA333ML Pin description (continued)
Type I/O GND Power I Name OUT1A GND_REG VDD_REG CONFIG N.C. N.C. N.C. N.C. VDD_DIG GND_DIG PWDN VDD_PLL FILTER_PLL GND_PLL XTI BICKI LRCKI SDI RESET INT_LINE ONSEL Description Output half bridge 1A Internal ground reference Internal 3.3 V reference voltage Paralleled mode command Not connected Not connected Not connected Not connected Positive supply digital Digital ground Power down: 0: low-power mode 1: normal operation Positive supply for PLL Connection to PLL filter Negative supply for PLL PLL input clock, 256 x fs or 384 x fs I2S serial clock I2S left/right clock I2S serial data channel Reset Fault interrupt Oversampling selector: 0: 256 fs 1: 384 fs Gain selector: 0: 0 dBFS 1: 24 dBFS Digital ground Digital supply
34 35 36
I GND Power
GAIN GND_DIG VDD_DIG
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STA333ML
Electrical specifications
3
3.1
Table 3.
Symbol RTh(j-case) Tsd Tw Thsd
Electrical specifications
Thermal data
Thermal data
Parameter Thermal resistance junction to case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis Min. Typ. 1.5 150 130 20 Max. 2 Unit C/W C C C
3.2
Table 4.
Symbol VCC VL VDD_DIG Top Tstg
Absolute maximum ratings
Absolute maximum ratings
Parameter Power supply voltage (VCC1, VCC2) Logic input interface Positive supply digital Operating junction temperature Storage temperature 0 -40 -0.3 Min. Typ. Max. 20 4 4 150 150 Unit V V V C C
3.3
Table 5.
Symbol VCC VL VDD_DIG Tamb
Recommended operating condition
Recommended operating condition
Parameter Power supply voltage (VCC1, VCC2) Logic Input Interface Positive supply digital Ambient temperature Min. 4.5 2.7 2.7 0 3.3 3.3 Typ. Max. 18.0 3.6 3.6 70 Unit V V V C
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Electrical specifications
STA333ML
3.4
Electrical characteristics
The specifications given here are with the operating conditions VCC = 18 V, VDD_DIG =3.3 V, fsw = 384 kHz, Tamb = 25 C and RL = 8 , unless otherwise specified.
Table 6.
Symbol Po
Electrical characteristics
Parameter Output power BTL THD = 10% 20 180 250 10 95 95 5 10 8 8 4.5 PWRDN = 0 PCM input signal = -60 dBFS. Switching frequency = 384 kHz No LC filters Internal clock = 49.152 MHz Nonlinear output Hi-Z output 2.2 2.7 0.1 10 20 10 10 18 m A % % ns ns ns ns V mA Power Pchannel/Nchannel MOSFET (total bridge) Power Pchannel/Nchannel leakage Conditions THD = 1% Min. Typ. 16 W Max. Unit
RdsON ldss gP gN ILDT IHDT tr tf VCC
ld = 1 A Vcc = 18 V
Power Pchannel RdsON matching ld = 1 A Power Nchannel RdsON matching ld = 1 A Low current dead time (static) High current dead time (dynamic) Rise time Fall time Supply voltage (VCC1, VCC2) Supply current from VCC in power down mode Resistive load, see Figure 3 lload = 1.5 A, see Figure 3 Resistive load, seeFigure 3 Resistive load, see Figure 3
Icc
Supply current from VCC in operation Supply current DDX processing (reference only)
30
mA
80 3.5 3.8 3.5 4.3 5.0 4.3 60
mA A A V ns dB dB 0.2 % dB
Ilim Isc UVL tmin DR SNR THD+N PSRR
Overcurrent limit Short circuit protection Under voltage protection threshold Output minimum pulse width Dynamic range Signal to noise ratio
No load
20
30 100
A-weighted
94 0.05 80
Total harmonic distortion and noise Po = 1 W, f = 1 kHz Power supply rejection ratio DDX stereo, < 5 kHz Vripple = 1 V RMS Audio input = dither only DDX stereo, < 5 kHz One channel driven at 1 W other channel measured Po = 2 x 20 W, 8
XTALK
Crosstalk Peak efficiency, DDX mode
80 90
dB %
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STA333ML
Electrical specifications
3.5
Testing
Figure 3. Test circuits
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B
DTout(A) M58 Q1 OUTA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTB M64
DTin(A) INA M57
DTin(B) INB M63
Iout=4A Lout = 1.5 A Q3
Iout=4A Lout = 1.5 A Q4
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D03AU1517
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Functional description
STA333ML
4
4.1
Functional description
Serial audio interface protocols
Figure 4. I2S
Lrclki
Bicki
Sdi
1 3 123
n-1 n
123
n-1 n
Figure 5.
Left justified
Lrclki/ Lrclko
Biclki/ Biclko
Sdatai/ Sdatao
123
n-1 n
123
n-1 n
4.2
Fault detect recovery bypass
The on-chip STA333ML power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tristate output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This sequence is repeated for as long as the fault exists.
4.3
Zero-detect mute enable
If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. If so the channel is muted.
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STA333ML
Package thermal characteristics
5
Package thermal characteristics
The amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. For the STA333ML the maximum dissipated power is approximately 3 W. Thus, at an ambient temperature of 70 C (the generally recommended maximum for consumer applications) the device can tolerate a further temperature rise of around 80 C before thermal shutdown is invoked (at Tj = 150 C). A suitable heatsink must, therefore, be found. Now, a thermal resistance of 25 C/W can be achieved using a ground copper area of 3 x 3 cm2, and 16 vias, on the PCB as shown in Figure 6. This gives a tiny margin of safety near to the upper recomended operating limits. Figure 6. Using the PCB as heatsink
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Package information
STA333ML
6
Package information
Figure 7 shows the 36-pin PowerSSO package drawing and Table 7 gives the dimensions. Figure 7. PowerSSO-36 slug down outline drawing
10/14
h x 45
STA333ML Table 7.
Symbol Min A A2 a1 b c D E e e3 F G H h k L M N O Q S T U X Y 2.15 2.15 0 0.18 0.23 10.10 7.40 10.10 0 0.60 4.10 6.50 0.5 8.5 2.3 4.30 1.20 0.80 2.90 3.65 1.00 Typ 2.47 2.40 0.10 0.36 0.32 10.50 7.60 0.10 10.50 0.40 8 degrees 1.00 10 degrees 4.70 7.10 0.161 0.256 0.024 Max Min 0.085 0.085 0 0.007 0.009 0.398 0.291 0.398 -
Package information PowerSSO-36 slug down dimensions
mm inch Typ Max 0.097 0.094 0.004 0.014 0.013 0.413 0.299
0.020 0.335 0.091 0.004 0.413 0.016 8 degrees 0.039 0.169 10 degrees 0.047 0.031 0.114 0.144 0.039 0.185 0.280
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Trademarks and other acknowledgements
STA333ML
7
Trademarks and other acknowledgements
DDX is a registered trademark of Apogee Technology Inc. Sound Terminal is a trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics.
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STA333ML
Revision history
8
Revision history
Table 8.
Date 2-May-2008 1-Feb-2007
Document revision history
Revision 2 1 Package information update Initial release. Changes
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STA333ML
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